Data storage systems utilize readback signals to calibrate a read head before reading. Zero phase start is used to provide an initial timing error estimate in frontend digital phase-locked-loop (DPLL) timing loop. When the readback signal includes defects, phase estimation is less reliable. Defects are currently handled by lengthening the sample window or shifting the sample window. Lengthening or shifting the sample window introduces undesirable latency.
Consequently, it would be advantageous if an apparatus existed that is suitable for producing a reliable zero phase start estimation from initial readback signal samples, regardless of defects.